01
Signal-attestation path
Source evidence, context binding, admission state, and verifier-facing receipts designed to survive movement from software prototype into a protected hardware path.
Living Cipher Hardware
Hardware is the product engine.
Living Cipher develops semiconductor IP and implementation paths for trust at the boundaries where signals, components, computations, and results become authorized participants in consequential systems.
The present path is concrete: FPGA, SoC, chiplet, post-quantum trust, physiological-signal attestation, RTL, implementation evidence, and eventual custom silicon. Research extends the same architecture questions to biological, quantum, and other non-silicon substrates.
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The substrate changes. The relying party's questions do not: what participated, under what state, with what evidence, and why should the result be trusted?
Hardware thesis
Current Hardware Program
Trust before compute, within compute, and after compute.
02
Trust plane
Enrollment, device and component identity, approved state, policy, quarantine, revocation, recovery, and authorization interfaces for heterogeneous systems.
03
Post-quantum datapaths
Custom cryptographic blocks implemented where long-lived evidence and trust decisions require hardware visibility rather than opaque third-party behavior.
04
Trusted chiplet composition
Producer/consumer authorization, component state, lifecycle, data-path control, and system-level evidence across boards, SoCs, chiplets, packages, and multi-die systems.
05
Physiological compute
Real-time DSP, multimodal signal ingestion, neural and physiological interfaces, model partitioning, and workload evidence that can inform FPGA-to-ASIC decisions.
06
Architecture-to-silicon
Requirements, RTL, simulation, synthesis, P&R, timing, FPGA bring-up, substrate selection, and pre-fabrication evidence before irreversible silicon commitment.
Architecture Principle
A trust path needs attachment points before it needs every final mechanism.
Boards and chiplets do not need to predict every future relying-party policy. They do need enough architecture to expose state, carry evidence, enforce authorization, and attach future trust logic without redesigning the compute datapath solely because deployment requirements arrived late.
01
Identity
What component or source is this?
02
State
What is it running and under which lifecycle?
03
Enrollment
Is it authorized for this composition and role?
04
Evidence
Can the relying system consume the required proof?
05
Enforcement
Can access, DMA, data, or compute be withheld?
06
Recovery
Can it be quarantined, revoked, updated, and re-admitted?
Implementation Ladder
Evidence determines what becomes silicon.
Software / reference
Learn the behavior
Characterize the signal, workload, algorithm, and verifier contract before hardening the wrong assumption.
FPGA / SoC
Measure reality
Close timing, observe resources and data movement, exercise trust hooks, and define what has earned permanence.
Chiplet / ASIC
Freeze only the stable substrate
Promote recurrent, economically justified functions while preserving programmability around changing intelligence and policy.
Production
Remain admissible
Carry identity, lifecycle, provenance, update, recovery, and target-specific evidence through manufacturing and deployment.
Evidence, Not Assertion
The architecture has to survive implementation.
53.4 MHz
Post-route ML-DSA performance at the slow, low-voltage, high-temperature corner on PolarFire SoC.
Zero
Vendor cryptographic cores in the custom datapath; the security-critical behavior remains inspectable at RTL.
End to end
Architecture carried through implementation evidence rather than stopping at a block diagram.
Beyond Conventional Silicon
The trust problem survives the substrate transition.
Living Cipher is not limited conceptually to CMOS. Biological computing, quantum hardware, neuromorphic systems, and hybrid electronic/non-electronic architectures make the same relying-party problem harder: what participated in the computation, what physical state mattered, what evidence survives the transformation, and who is authorized to act on the result?
Current implementation remains centered on conventional FPGA, SoC, chiplet, and future ASIC paths. Emerging-substrate work is a research horizon, not a claim of production biological or quantum hardware.